Topic: CPU components

PSX CPU consists of the following components :

- R3000A core with bogus COP0 MMU
- 3 root counters (two of them can be connected to GPU pixel clock and HBLANK)
- Data cache configured as fast RAM ("scratch pad")
- Instruction cache (with "isolate" ability)
- Some weird and mysterious 0xFFFE0130 register
- RAS/CAS controller for CPU DRAM and Bus Unit to distribute memory access and DMA transfers
- Memory access timing registers (configured in BIOS)
- serial interface with SIO0 (controllers/memcards) and SIO1 (external port)
- parallel interface (for extra device on SBUS)
- DMA controller
- interrupt controller
- GTE as COP2 (fixed point math)
- MDEC (motion picture decompressor, again fixed point math)

The most complicated thing is Bus Unit (B/U), which handle complex task to grant access to various internal devices for two external buses : Sub-Bus and Main bus.

Sub-bus connects CPU with PSX SUB-system (CDROM decoder, SPU, BIOS and PIO). Main bus connects CPU with DRAM and GPU. All things are act together under PSX CPU Bus Unit sofisticated control.

Re: CPU components

The RISC core is actually an LR33300 from LSI; here are the first four chapters of its manual:
Unfortunately, I couldn't find the rest online anywhere. However, the "L64360" uses the same RISC core and describes a few of its registers; the mysterious register 0xfffe0130 is explained on page 14-7 of the manual. I tested a few of its bits a while back, and it definitely is the same register. For example, I could turn "load scheduling" on and off with bit 16.

Re: CPU components

Thanks, I put it here smile

Re: CPU components

Cool. Good finding! Very nice to see official specs for FFFF0130 cache control, and for the COP0 debug registers!