Topic: ICache and DCache

Second american decaper made M1 slice so we now able to revengineer "block units", which are located around CPU border (in general its usual Verilog buffers - reg buffer[size])

Some of them are I-Cache (4096 byte) and D-Cache (1024 byte):

Memory type is conventional SRAM, based on 6-transistor SRAM-cells:

Re: ICache and DCache

Latest research on Dcache control: